1. Field of the Invention
The present invention relates to an electrically erasable and programmable non-volatile memory device. More particularly, the present invention relates to a non-volatile memory device in which a threshold voltage is controlled to relax electrical stress with respect to a memory cell transistor, thereby improving the number of rewrite operations.
2. Description of the Background Art
As electrically erasable and programmable non-volatile memory devices, EEPROM (Electrically Erasable Programmable Read Only Memory) and flash EEPROM are known, as disclosed in, for example, Japanese Patent Laid-Open Publication No. 2002-208291. FIG. 19 is a diagram illustrating a structure of a flash EEPROM described in the above-described publication. The flash EEPROM 1900 of FIG. 19 comprises a memory cell array 1910, a booster circuit 140, a regulator circuit 150, a decoder circuit 160, a read determination circuit 170, and a control circuit 180.
The memory cell array 1910 includes a plurality of memory cell transistors which are arranged in an array. Each memory cell transistor has a floating gate for accumulating electric charge so as to store data in a non-volatile manner. The memory cell transistor is subjected to a step of injecting electric charge into the floating gate (hereinafter referred to as a “write operation”) and a step of releasing electric charge accumulated in the floating gate (hereinafter referred to as an “erase operation”). Hereinafter, a combination of the “erase operation” and the “write operation” is referred to as a “rewrite operation”.
Among the above-described two steps with respect to a memory cell transistor, the erase operation is performed in units of a plurality of memory cell transistors which can be simultaneously selected, such as a row or column in the memory cell array 1910. A set of a plurality of memory cell transistors which can be simultaneously selected and erased in the above-described manner are referred to as an “erase unit area”. The memory cell array 1910 of FIG. 19 includes n erase unit areas 121 to 12N. In addition to this, the memory cell array 1910 includes a trimming value storing area 1930 described below.
Generally, in a flash EEPROM, in order to perform an erase operation or a write operation with respect to a memory cell transistor, voltages higher than a power source voltage are required (hereinafter referred to as an “erase voltage” and a “write voltage”, respectively, and both the voltages are collectively referred to as an “erase/write voltage”). To this end, the flash EEPROM 1900 includes the booster circuit 140.
In the flash EEPROM 1900, a rewrite operation is performed with respect to a memory cell transistor as follows. When the rewrite operation is performed, an address of an erase unit area 120 to be rewritten and data to be written are input via an I/O buffer (not shown). The decoder circuit 160 selects a bit line and a word line (not shown) based on the input address. As a result, the erase unit area 120 to be rewritten is selected. The booster circuit 140 boosts the power source voltage to the erase/write voltage. The trimming value storing area 1930 is a non-volatile memory area included in the memory cell array 1910, which stores an output regulating value (hereinafter referred to as a “trimming value”) for the erase/write voltage. In the trimming value storing area 1930, an appropriate trimming value is previously set as an initial value. The regulator circuit 150 regulates a level of the erase/write voltage based on the trimming value stored in the trimming value storing area 1930. The read determination circuit 170 performs a determination step with respect to the threshold voltage of a memory cell transistor after performing a rewrite operation with respect to the erase unit area 120. The control circuit 180 controls each portion of the flash EEPROM 1900.
In an erase operation, an erase voltage whose level is regulated by the regulator circuit 150 is applied to the erase unit area 120 selected by the decoder circuit 160. In a memory cell transistor to which the erase voltage is applied, electric charge accumulated at the floating gate is released, so that a threshold voltage Vt thereof decreases. Such a state of the memory cell transistor is referred to as an “erased state”. The erased state corresponds to a logical state in which data “1” is stored.
In a write operation, a write voltage whose level is regulated by the regulator circuit 150 is applied to the erase unit area 120 selected by the decoder circuit 160. In a memory cell transistor to which the write voltage is applied, electric charge is externally injected into the floating gate to increase the threshold voltage Vt. Such a state of the memory cell transistor is referred to as a “written state”. The written state corresponds to a logical state in which data “0” is stored.
In the flash EEPROM 1900, when the write operation is repeatedly performed with respect to a memory cell transistor, characteristics of the memory cell transistor are gradually degraded, leading to a change in the threshold voltage of the memory cell transistor. FIG. 20 is a diagram illustrating a relationship between the number of rewrite operations in the flash EEPROM 1900 and the threshold voltage Vt. In FIG. 20, the horizontal axis represents the number of rewrite operations, while the vertical axis represents the threshold voltage of a memory cell transistor.
Characteristics indicated with solid lines will be first described. When a rewrite operation is repeatedly performed with respect to a memory cell transistor, a threshold voltage V0 after a write operation gradually decreases, while a threshold voltage V1 after an erase operation gradually increases, as illustrated with the solid lines in FIG. 20. When these threshold voltages depart from correct values in their respective initial states, data accumulated in the memory cell transistor can be no longer correctly read out.
To prevent such a read error, the flash EEPROM 1900 changes an erase/write voltage to a higher value than before, when detecting a degradation in the characteristics of the memory cell transistor. For example, the read determination circuit 170, when the threshold voltage V1 after an erase operation exceeds a reference voltage Vx, determines that an abnormality occurs. When the read determination circuit 170 determines that an abnormality occurs, the control circuit 180 changes the trimming value stored in the trimming value storing area 1930 to a value which causes an erase/write voltage output from the regulator circuit 150 to be higher than before.
In the example of FIG. 20, when the number of rewrite operations reaches N1, the threshold voltage V1 after an erase operation exceeds the reference voltage Vx, and it is determined that an abnormality occurs. At this time, the trimming value stored in the trimming value storing area 1930 is updated to a value which causes an erase/write voltage output from the regulator circuit 150 to be higher than before. Thereby, the erase/write voltage output from the regulator circuit 150 is caused to be higher than before, so that the threshold voltage V0 after a write operation and the threshold voltage V1 after an erase operation are restored to levels which prevent a read error.
After the number of rewrite operations exceeds N1, the threshold voltage V0 after a write operation still gradually decreases, while the threshold voltage V1 after an erase operation still gradually increases. When the number of rewrite operations eventually reaches N2, the threshold voltage V1 after an erase operation exceeds the reference voltage Vx again, so that it is determined again that an abnormality occurs. At this time, the same step as when the number of rewrite operations reaches N1 is performed, an erase/write voltage output from the regulator circuit 150 is caused to be even higher, so that the threshold voltage V0 after a write operation and the threshold voltage V1 after an erase operation are restored again to levels which prevent a read error.
By controlling the trimming value in the above-described manner, even when a rewrite operation is repeatedly performed with respect to a memory cell transistor, the apparent characteristics of the memory cell transistor are maintained to be in the same state as when the number of rewrite operations is small. Therefore, according to the flash EEPROM 1900, the number of rewrite operations can be improved.
However, a rewrite operation with respect to a memory cell transistor may not be uniformly performed for all erase unit areas, i.e., the number of rewrite operations may vary among erase unit areas. In spite of this, the above-described conventional flash EEPROM 1900 employs a single trimming value to control the threshold voltages of all memory cell transistors included in the memory cell array. Therefore, when the number of rewrite operations varies among erase unit areas, the number of rewrite operations may not be satisfactorily improved.
This point will be described with reference to the characteristics indicated with dashed lines in FIG. 20. For example, the flash EEPROM 1900 is assumed to include an erase unit area having a large number of rewrite operations and an erase unit area having a small number of rewrite operations. In this case, for the erase unit area having a large number of rewrite operations, the apparent characteristics of the memory cell transistor can be maintained to be in a satisfactory state by controlling the trimming value. However, in the flash EEPROM 1900, updating of the trimming value also has an influence on the erase unit area having a small number of rewrite operations. Therefore, for a memory cell transistor included in the erase unit area having a small number of rewrite operations, the trimming value is updated before the characteristics are not much degraded, and every time the trimming value is updated, the threshold voltage V0 after a write operation and the threshold voltage V1 after an erase operation gradually depart from appropriate values in their respective initial values (see the dashed lines in FIG. 20).
As described above, in the flash EEPROM 1900, a memory cell transistor included in the erase unit area having a small number of rewrite operations may acquire abnormal erase and write characteristics. However, when an excessive erase/write voltage is applied to a memory cell transistor, the overall amount of electricity passing through a tunnel oxide film provided below the floating gate of the memory cell transistor increases, so that an electric field higher than necessary is applied. Due to electrical stress during such a rewrite operation, the life span of a memory cell transistor included in the erase unit area having a small number of rewrite operations may be shortened.